1. Field of the Invention
The present invention relates to a nonvolatile ferroelectric memory device, and more particularly, to a nonvolatile ferroelectric memory device and a method for fabricating the same.
2. Background of the Related Art
Generally, a nonvolatile ferroelectric memory, i.e., a ferroelectric random access memory (FRAM) has a data processing speed equal to a dynamic random access memory (DRAM) and retains data even in power off. For this reason, the nonvolatile ferroelectric memory has received much attention as a next generation memory device.
The FRAM and DRAM are memory devices with similar structures, but the FRAM includes a ferroelectric capacitor having a high residual polarization characteristic. The residual polarization characteristic permits data to be maintained even if an electric field is removed.
FIG. 1 shows hysteresis loop of a general ferroelectric. As shown in FIG. 1, even if polarization induced by the electric field has the electric field removed, data is maintained at a certain amount (i.e., d and a states) without being erased due to the presence of residual polarization (or spontaneous polarization). A nonvolatile ferroelectric memory cell is used as a memory device by corresponding the d and a states to 1 and 0, respectively.
A related art nonvolatile ferroelectric memory device will now be described. FIG. 2 shows unit cell of a related art nonvolatile ferroelectric memory.
As shown in FIG. 2, the related art nonvolatile ferroelectric memory includes a bitline B/L formed in one direction, a wordline W/L formed to cross the bitline, a plate line P/L spaced apart from the wordline in the same direction as the wordline, a transistor T1 with a gate connected with the wordline and a source connected with the bitline, and a ferroelectric capacitor FC1. A first terminal of the ferroelectric capacitor FC1 is connected with a drain of the transistor T1 and second terminal is connected with the plate line P/L.
The data input/output operation of the related art nonvolatile ferroelectric memory device will now be described. FIG. 3a is a timing chart illustrating the operation of the write mode of the related art nonvolatile ferroelectric memory device, and FIG. 3b is a timing chart illustrating the operation of read mode thereof.
During the write mode, an externally applied chip enable signal CSBpad is activated from high state to low state. At the same time, if a write enable signal WEBpad is applied from high state to low state, the write mode starts. Subsequently, if address decoding in the write mode starts, a pulse applied to a corresponding wordline is transited from low state to high state to select a cell.
A high signal in a certain period and a low signal in a certain period are sequentially applied to a corresponding plate line in a period where the wordline is maintained at high state. To write a logic value “1” or “0” in the selected cell, a high signal or low signal synchronized with the write enable signal WEBpad is applied to a corresponding bitline.
In other words, a high signal is applied to the bitline, and if the low signal is applied to the plate line in a period where the signal applied to the wordline is high, a logic value “1” is written in the ferroelectric capacitor. A low signal is applied to the bitline, and if the signal applied to the plate line is high, a logic value “0” is written in the ferroelectric capacitor.
With reference to FIG. 3b, the reading operation of data stored in a cell by the above operation of the write mode will now be described. If an externally applied chip enable signal CSBpad is activated from high state to low state, all of bitlines become equipotential to low voltage by an equalizer signal EQ before a corresponding wordline is selected.
Then, the respective bitline becomes inactive and an address is decoded. The low signal is transited to the high signal in the corresponding wordline according to the decoded address so that a corresponding cell is selected.
The high signal is applied to the plate line of the selected cell to destroy data corresponding to the logic value “1” stored in the ferroelectric memory. If the logic value “0” is stored in the ferroelectric memory, the corresponding data is not destroyed.
The destroyed data and the data that is not destroyed are output as different values by the ferroelectric hysteresis loop, so that a sensing amplifier senses the logic value “1” or “0”. In other words, if the data is destroyed, the “d” state is transited to an “f” state as shown in hysteresis loop of FIG. 1. If the data is not destroyed, “a” state is transited to the “f” state. Thus, if the sensing amplifier is enabled after a set time has elapsed, the logic value “1” is output in case that the data is destroyed while the logic value “0” is output in case that the data is not destroyed.
As described above, after the sensing amplifier outputs data, to recover the data to the original data, the plate line becomes inactive from high state to low state at the state that the high signal is applied to the corresponding wordline.
A related art nonvolatile ferroelectric memory and a method for fabricating the nonvolatile ferroelectric memory will now be described. FIG. 4a is a diagram that illustrates a layout of a related art nonvolatile ferroelectric memory.
Referring to FIG. 4a, the related art nonvolatile ferroelectric memory is provided with a first active region 41 and a second active region 41a asymmetrically formed at fixed intervals. A first wordline W/L1 is formed to cross the first active region 41, and a second wordline W/L2 is formed to cross the second active region 41a spaced a distance from the first wordline W/L1. A first bitline B/L1 is formed in a direction to cross the first and second wordlines at one side of the first active region 41, and a second bitline B/L2 is formed parallel to the first bitline B/L1 to cross the first and second wordlines at one side of the second active region 41a. A first ferroelectric capacitor FC1 is formed over the first wordline W/L1 and the second wordline W/L2 and is connected to the first active region 41. A second ferroelectric capacitor FC2 is formed over the first wordline W/L1 and is electrically connected to the second active region 41a. A first plate line P/L1 is formed over the first wordline W/L1 and is electrically connected to the first ferroelectric capacitor FC1, and a second plate line P/L2 is formed over the second wordline W/L2 and is electrically connected to the second ferroelectric capacitor FC2. FIG. 4a is a diagram that illustrates a layout of a unit cell, wherein the related art nonvolatile ferroelectric memory has the first and second ferroelectric capacitors FC1 and FC2 formed extending along a bitline direction, and the first plateline P/L1 formed over the first wordline W/L1 and the second plateline P/L2 formed over the second wordline W/L2.
FIG. 4b is a diagram that illustrates a cross-section across line I-I′ in FIG. 4a. Referring to FIG. 4b, the related art nonvolatile ferroelectric memory is provided with a substrate 51 having an active region and a field region defined thereon, a first wordline 54 and a second wordline 54a formed over the active region and the field region with a first insulating layer 53 disposed inbetween, and first source/drain impurity regions 55 and 56 formed on both sides of the first wordline 54. Second source/drain impurity regions (not shown) are formed on both sides of the second wordline 54a. A second insulating layer 57 is formed on an entire surface inclusive of the first and second wordlines 54 and 54a having a contact hole exposing the first drain impurity region 56, and a first plug layer 58a is stuffed in the contact hole. A first metal layer 59 connects the first plug layer 58a and the first bitline (not shown). A third insulating layer 60 is formed on an entire surface inclusive of the first metal layer 59 having a contact hole exposing the first source impurity region 55, and a second plug layer 62 is stuffed in the contact hole. A barrier metal layer 63 is electrically connected to the second plug layer 62 and extended horizontally over the first wordline to the second wordline 54a. A lower electrode 64 of the first ferroelectric capacitor FC1 is formed on the barrier metal layer 63, a ferroelectric film 65 and an upper electrode 66 of the first ferroelectric capacitor are stacked on the lower electrode 64 of the first ferroelectric capacitor FC1 in succession. A fourth insulating layer 67 is formed on an entire surface inclusive of the upper electrode 66 of the second ferroelectric capacitor. A first plate line 68 is formed over the first wordline 54 and electrically connected to the upper electrode 66 of the first ferroelectric capacitor FC1 through the fourth insulating layer, and a second plate line 68a formed over the second wordline 54a spaced from the first plate line 68.
A method for fabricating the related art nonvolatile ferroelectric memory of FIGS. 4a-4b will now be described. FIGS. 5a˜5f are diagrams that illustrate cross-sections showing the steps of a method for fabricating the related art nonvolatile ferroelectric memory shown along line I-I′ in FIG. 4a. As shown in FIG. 5a, a portion of a semiconductor substrate 51 is etched to form a trench, and an insulating film is stuffed in the trench to form a device isolation layer 52. A first insulating layer 53 is formed on the substrate in the active region inclusive of the device isolation layer 52. A wordline material layer is formed on the first insulating layer 53, and patterned to form first and second wordlines 54 and 54a at fixed intervals.
As shown in FIG. 5b, the wordlines 54 and 54a are used as masks in implanting impurity ions to form a source impurity region 55 and a drain impurity region 56 having a conduction type opposite to the substrate 51. The source/drain impurity regions 55 and 56 are source/drain impurity regions of the first transistor T1 that takes the first wordline 54 as a gate electrode: Then, a second insulating layer 57 is formed on an entire surface of the substrate 51 inclusive of the first and second wordlines 54 and 54a. A photoresist layer (not shown) is coated on the second insulating layer 55 and patterned, and the patterned photoresist layer is used as a mask in selectively etching the second insulating layer 57 to form a contact hole 58 exposing the drain impurity region 56.
As shown in FIG. 5c, a conductive material is stuffed in the contact hole to form a first plug layer 58a, and first metal layer 59 is formed to connect the first plug layer 58a and the first bitline B/L1. Though not shown, the second bitline B/L2 is electrically connected to the drain impurity region of the second transistor T2.
As shown in FIG. 5d, a third insulating layer 60 is formed on an entire surface inclusive of the first metal layer 59. A photoresist layer (not shown) is coated on the third insulating layer 60, patterned and used as mask in selectively etching the third insulating layer to form a contact hole 61 exposing the source impurity region 55.
As shown in FIG. 5e, a conductive material is stuffed in the contact hole 61 to form a second plug layer 62 electrically connected to the source impurity region 55. A barrier metal layer 63 is formed to be electrically connected to the second plug layer 62 and a lower electrode 64 of the first ferroelectric capacitor FC1. The lower electrode 64, a ferroelectric film 65 and upper electrode 66 of the first ferroelectric capacitor are successively formed on the barrier metal layer 63.
As shown in FIG. 5f, a fourth insulating layer 67 is formed on the upper electrode 66 of the first ferroelectric capacitor and selectively etched by photolithography to form a contact hole exposing a portion of the upper electrode 66 of the first ferroelectric capacitor FC1. Upon formation of a first plate line 68 connected with the upper electrode 66 of the first ferroelectric capacitor through the contact hole, the related art process for fabricating nonvolatile ferroelectric memory is completed. A second plate line 68a is also shown in FIG. 5f. 
As described above, the related art nonvolatile ferroelectric memory and the related art method for fabricating the same have various disadvantages. A requirement to form the lower electrode of a capacitor thicker for increasing a sectional area of the lower electrode for securing capacitance causes a problem in that etching of the lower electrode is difficult because the lower electrode of the capacitor is formed of metal. Further, the fabrication process is very difficult because the plate line should be formed in a small space so that a sufficient space is secured distinguishing the plate line from a wordline in an adjacent cell as the wordline and the plate line are formed in every unit cell. The small space complicates the corresponding process steps. Further, since an upper electrode of the ferroelectric capacitor and the plate line are connected with each other through the contact hole, the number of masks for the formation of the contact hole increases. A related cost of fabrication and a final product increases with each mask.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.